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features n 10-bit resolution n 20/40/65/80msps maximum sampling rate n ultra-low power dissipation: 24/43/65/78mw n 61.6db snr at 80msps and 8mhz f in n internal reference circuitry n 1.8v core supply voltage n 1.7v C 3.6v i/o supply voltage n parallel cmos output n 64-pin qfn package n dual channel n pin compatible with cdk2307 applications n medical imaging n portable test equipment n digital oscilloscopes n if communication general description the cdk2308 is a high performance, low power dual analog-to-digital con - verters (adc). the adc employs internal reference circuitry, a cmos control interface and cmos output data, and is based on a proprietary structure. digital error correction is employed to ensure no missing codes in the com - plete full scale range. several idle modes with fast startup times exist. each channel can indepen - dently be powered down and the entire chip can either be put in standby mode or power down mode. the different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. the cdk2308 has a highly linear tha optimized for frequencies up to nyquist. the differential clock interface is optimized for low jitter clock sources and supports lvds, lvpecl, sine wave and cmos clock inputs. functional block diagram ordering information part number speed package pb-free rohs compliant operating temperature range packaging method CDK2308AILP64 20msps qfn-64 yes yes -40c to +85c tray cdk2308bilp64 40msps qfn-64 yes yes -40c to +85c tray cdk2308cilp64 65msps qfn-64 yes yes -40c to +85c tray cdk2308dilp64 80msps qfn-64 yes yes -40c to +85c tray moisture sensitivity level for all parts is msl-2a. clk_ext 10 10 clkp clkn data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters exar corporation www.exar.com 48720 kato road, fremont ca 94538, usa tel. +1 510 668-7000 - fax. +1 510 668-7001
?2009-2013 exar corporation 2/15 rev 2b pin assignments pin no. pin name description 1, 18, 23 dv dd digital and i/o-ring pre driver supply voltage, 1.8v 2 cm_ext common mode voltage output 3, 9, 12 av dd analog supply voltage, 1.8v 4, 5, 8 av ss analog ground 6, 7 ip0, in0 analog input channel 0 (non-inverting, inverting) 10, 11 ip1, in1 analog input channel 1 (non-inverting, inverting) 13 dv ssclk clock circuitry ground 14 dv ddclk clock circuitry supply voltage, 1.8v 15 clkp clock input, non-inverting (format: lvds, pecl, cmos/ttl, sine wave) 16 clkn clock input, inverting. for cmos input on clkp, connect clkn to ground 17, 64 dv ss digital circuitry ground 19 clk_ext_en clk_ext signal enabled when low (zero). tristate when high. 20 d frmt data format selection. 0: offset binary, 1: two's complement 21 pd_n full chip power down mode when low. all digital outputs reset to zero. after chip power up, always apply power down mode before using active mode to reset chip. 22 oe_n_1 output enable channel 0. tristate when high 24, 41, 58 o vdd i/o ring post-driver supply voltage. voltage range 1.7v to 3.6v. 25, 40, 57 o vss ground for i/o ring pin confguration qfn-64, tqfp-64 cdk2308 qfn-64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 n/c n/c n/c 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 n/c n/c n/c 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 d0_5 d0_4 d0_3 dvddclk clk_ext_en clkn clkp dvssclk clk_ext data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 3/15 rev 2b pin no. pin name description 26 nc no connect 27 nc no connect 28 nc no connect 29 d1_0 output data channel 1 (lsb) 30 d1_1 output data channel 1 31 d1_2 output data channel 1 32 d1_3 output data channel 1 33 d1_4 output data channel 1 34 d1_5 output data channel 1 35 d1_6 output data channel 1 36 d1_7 output data channel 1 37 d1_8 output data channel 1 38 d1_9 output data channel 1 (msb) 39 orng_1 out of range fag channel 1. high when input signal is out of range 42 clk_ext output clock signal for data synchronization. cmos levels. 43 nc no connect 44 nc no connect 45 nc no connect 46 d0_0 output data channel 0 47 d0_1 output data channel 0 48 d0_2 output data channel 0 49 d0_3 output data channel 0 50 d0_4 output data channel 0 51 d0_5 output data channel 0 52 d0_6 output data channel 0 53 d0_7 output data channel 0 54 d0_8 output data channel 0 55 d0_9 output data channel 0 (msb) 56 orng_0 out of range fag channel 0. high when input signal is out of range. 59 oe_n_0 output enable channel 0. tristate when low. 60, 61 cm_extbc_1, cm_extbc_0 bias control bits for the buffer driving pin cm_ext 00: off 01: 50ua 10: 500ua 11: 1ma 62, 63 slp_n_1, slp_n_0 sleep mode 00: sleep mode 01: channel 0 active 10: channel 1 active 11: both channels active pin assignments (continued) data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 4/15 rev 2b absolute maximum ratings the safety of the device is not guaranteed when it is operated above the absolute maximum ratings. the device should not be operated at these absolute limits. adhere to the recommended operating conditions for proper device function. the information contained in the electrical characteristics tables and typical performance plots refect the operating conditions noted on the tables and plots. parameter min max unit av dd , av ss -0.3 +2.3 v dv dd , dv ss -0.3 +2.3 v av ss , dv ssck , dv ss , ov ss -0.3 +0.3 v ov dd , ov ss -0.3 +3.9 v ckp, ckn, dv ssck -0.3 +3.9 v analog inputs and outpts (ipx, inx, av ss ) -0.3 +2.3 v digital inputs -0.3 +3.9 v digital outputs -0.3 +3.9 v reliability information parameter min typ max unit storage temperature range -60 +150 c lead temperature (soldering, 10s) j-std-020 esd protection product qfn-64 tqfp-64 human body model (hbm) 2kv 2kv recommended operating conditions parameter min typ max unit operating temperature range -40 +85 c data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 5/15 rev 2b electrical characteristics (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 50msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units dc accuracy no missing codes guaranteed offset error midscale offset 1 lsb gain error full scale range deviation from typical -6 6 %fs gain matching gain matching between channels 0.05 %fs dnl differential non-linearity 12-bit level 0.15 lsb ile integral non-linearity 12-bit level 0.2 lsb v cmo common mode voltage output v avdd /2 v analog input v cmi input common mode analog input common mode voltage v cm -0.1 v cm +0.2 v v fsr full scale range differential input voltage range 2 vpp input capacitance differential input capacitance 2 pf bandwidth input bandwidth, full power 500 mhz power supply av dd , dv dd core supply voltage supply voltage to all 1.8v domain pins. see pin confguration and description 1.7 1.8 2.0 v ov dd i/o supply voltage output driver supply voltage (ov dd ). must be higher than or equal to core supply voltage (vov dd vdv dd ) 1.7 2.5 3.6 v data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 6/15 rev 2b electrical characteristics - cdk2308a (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 20msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 2mhz 61.7 dbfs f in = 8mhz 60 61.6 dbfs f in ? fs/2 61.6 dbfs f in = 20mhz 61.6 dbfs sndr signal to noise and distortion ratio f in = 2mhz 61.7 dbfs f in = 8mhz 60 61.6 dbfs f in ? fs/2 60.5 dbfs f in = 20mhz 61.6 dbfs sfdr spurious free dynamic range f in = 2mhz 80 dbc f in = 8mhz 70 81 dbc f in ? fs/2 70 dbc f in = 20mhz 80 dbc hd2 second order harmonic distortion f in = 2mhz -90 dbc f in = 8mhz -80 -90 dbc f in ? fs/2 -90 dbc f in = 20mhz -90 dbc hd3 third order harmonic distortion f in = 2mhz -80 dbc f in = 8mhz -70 -81 dbc f in ? fs/2 -70 dbc f in = 20mhz -80 dbc enob effective number of bits f in = 2mhz 10 bits f in = 8mhz 9.7 9.9 bits f in ? fs/2 9.8 bits f in = 20mhz 9.9 bits x talk crosstalk signal crosstalk between channels, f in1 = 8mhz, f in0 = 9.9mhz -105 dbc power supply ai dd analog supply current 8.2 ma di dd digital supply current digital core supply 1.7 ma oi dd output driver supply 2.5v output driver supply, sine wave input, f in = 1mhz 2.8 ma 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext disabled 2.3 ma analog power dissipation 14.8 mw digital power dissipation ov dd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 8.8 mw total power dissipation ov dd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 23.6 mw power down dissipation 9.9 w sleep mode 1 power dissipation, sleep mode one channel 15.2 mw sleep mode 2 power dissipation, sleep mode both channels 7.7 mw clock inputs max. conversion rate 20 msps min. conversion rate 15 msps data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 7/15 rev 2b electrical characteristics - cdk2308b (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 40msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 2mhz 61.6 dbfs f in = 8mhz 60 61.6 dbfs f in ? fs/2 61.6 dbfs f in = 30mhz 61.5 dbfs sndr signal to noise and distortion ratio f in = 2mhz 61.6 dbfs f in = 8mhz 60 61.6 dbfs f in ? fs/2 61.2 dbfs f in = 30mhz 61.4 dbfs sfdr spurious free dynamic range f in = 2mhz 80 dbc f in = 8mhz 70 81 dbc f in ? fs/2 72 dbc f in = 30mhz 80 dbc hd2 second order harmonic distortion f in = 2mhz -90 dbc f in = 8mhz -80 -90 dbc f in ? fs/2 -85 dbc f in = 30mhz -85 dbc hd3 third order harmonic distortion f in = 2mhz -80 dbc f in = 8mhz -70 -81 dbc f in ? fs/2 -72 dbc f in = 30mhz -80 dbc enob effective number of bits f in = 2mhz 9.9 bits f in = 8mhz 9.7 9.9 bits f in ? fs/2 9.9 bits f in = 30mhz 9.9 bits x talk crosstalk signal crosstalk between channels, f in1 = 8mhz, f in0 = 9.9mhz -100 dbc power supply ai dd analog supply current 14.4 ma di dd digital supply current digital core supply 3.4 ma oi dd output driver supply 2.5v output driver supply, sine wave input, f in = 1mhz 5.1 ma 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext disabled 4.2 ma analog power dissipation 25.9 mw digital power dissipation ov dd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 16.6 mw total power dissipation ov dd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 42.5 mw power down dissipation 9.7 w sleep mode 1 power dissipation, sleep mode one channel 25.7 mw sleep mode 2 power dissipation, sleep mode both channels 11.3 mw clock inputs max. conversion rate 40 msps min. conversion rate 20 msps data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 8/15 rev 2b electrical characteristics - cdk2308c (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd=2.5v, 65msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 8mhz 60 61.6 dbfs f in = 20mhz 61.6 dbfs f in ? fs/2 61.5 dbfs f in = 40mhz 61.3 dbfs sndr signal to noise and distortion ratio f in = 8mhz 60 61.6 dbfs f in = 20mhz 61.6 dbfs f in ? fs/2 60.4 dbfs f in = 40mhz 61.1 dbfs sfdr spurious free dynamic range f in = 8mhz 70 77 dbc f in = 20mhz 77 dbc f in ? fs/2 70 dbc f in = 40mhz 75 dbc hd2 second order harmonic distortion f in = 8mhz -80 -90 dbc f in = 20mhz -95 dbc f in ? fs/2 -85 dbc f in = 40mhz -90 dbc hd3 third order harmonic distortion f in = 8mhz -70 -77 dbc f in = 20mhz -77 dbc f in ? fs/2 -70 dbc f in = 40mhz -75 dbc enob effective number of bits f in = 8mhz 9.7 9.9 bits f in = 20mhz 9.9 bits f in ? fs/2 9.7 bits f in = 40mhz 9.9 bits x talk crosstalk signal crosstalk between channels, f in1 = 8mhz, f in0 = 9.9mhz -97 dbc power supply ai dd analog supply current 22 ma di dd digital supply current digital core supply 5.2 ma oi dd output driver supply 2.5v output driver supply, sine wave input, f in = 1mhz 7.9 ma 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext disabled 6.4 ma analog power dissipation 39.6 mw digital power dissipation ov dd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 25.4 mw total power dissipation ov dd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 65 mw power down dissipation 9.3 w sleep mode 1 power dissipation, sleep mode one channel 38.2 mw sleep mode 2 power dissipation, sleep mode both channels 15.7 mw clock inputs max. conversion rate 65 msps min. conversion rate 40 msps data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 9/15 rev 2b electrical characteristics - cdk2308d (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 80msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 8mhz 60 61.6 dbfs f in = 20mhz 61.2 dbfs f in = 30mhz 61.3 dbfs f in ? fs/2 61.3 dbfs sndr signal to noise and distortion ratio f in = 8mhz 60 61.3 dbfs f in = 20mhz 60.7 dbfs f in = 30mhz 61 dbfs f in ? fs/2 59 dbfs sfdr spurious free dynamic range f in = 8mhz 70 75 dbc f in = 20mhz 75 dbc f in = 30mhz 75 dbc f in ? fs/2 65 dbc hd2 second order harmonic distortion f in = 8mhz -80 -90 dbc f in = 20mhz -95 dbc f in = 30mhz -90 dbc f in ? fs/2 -80 dbc hd3 third order harmonic distortion f in = 8mhz -70 -75 dbc f in = 20mhz -75 dbc f in = 30mhz -75 dbc f in ? fs/2 -65 dbc enob effective number of bits f in = 8mhz 9.7 9.9 bits f in = 20mhz 9.8 bits f in = 30mhz 9.8 bits f in ? fs/2 9.5 bits x talk crosstalk signal crosstalk between channels, f in1 = 8mhz, f in0 = 9.9mhz -95 dbc power supply ai dd analog supply current 26.5 ma di dd digital supply current digital core supply 6.1 ma oi dd output driver supply 2.5v output driver supply, sine wave input, f in = 1mhz 9.5 ma 2.5v output driver supply, sine wave input, f in = 1mhz, clk_ext disabled 7.6 ma analog power dissipation 47.7 mw digital power dissipation ov dd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 30 mw total power dissipation ov dd = 2.5v, 5pf load on output bits, f in = 1mhz, clk_ext disabled 77.7 mw power down dissipation 9.1 w sleep mode 1 power dissipation, sleep mode one channel 46.1 mw sleep mode 2 power dissipation, sleep mode both channels 18.3 mw clock inputs max. conversion rate 80 msps min. conversion rate 65 msps data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 10/15 rev 2b digital and timing electrical characteristics (avdd = 1.8v, dvdd = 1.8v, dvddclk = 1.8v, ovdd = 2.5v, 50 msps clock, 50% clock duty cycle, -1 dbfs input signal, 5pf capacitive load, unless otherwise noted) symbol parameter conditions min typ max units clock inputs duty cycle 20 80 % high compliance cmos, lvds, lvpecl, sine wave input range differential input swing 400 mvpp differential input swing, sine wave clock input 1.6 vpp input common mode voltage keep voltages within ground and voltage of ov dd 0.3 v ovdd -0.3 v input capacitance differential 2 pf timing t pd start up time active mode from power down mode to active mode 900 clk cycles t slp start up time mode from sleep mode to active mode 20 clk cycles t ovr out of range recovery time 1 clk cycles t ap aperture delay 0.8 ns rms aperture jitter <0.5 ps t lat pipeline delay 12 clk cycles t d output delay (see timing diagram) 5pf load on output bits 4 ns t dc output delay (see timing diagram) relative to clk_ext 2 ns logic inputs v ih high level input voltage v ovdd 3.0v 2 v v ovdd = 1.7v C 3.0v 0.8 ? v ovdd v v il low level input voltage v ovdd 3.0v 0 0.8 v v ovdd = 1.7v C 3.0v 0 0.2 ? v ovdd v i ih high level input leakage current -10 10 a i il low level input leakage current -10 10 a c i input capacitance 3 pf logic outputs v oh high level output voltage v ovdd -0.1 v v ol low level output voltage 0.1 v c l max capacitive load post-driver supply voltage equal to pre-driver supply voltage v ovdd = v ocvdd 5 pf post-driver supply voltage above 2.25v (1) 10 pf note: (1) the outputs will be functional with higher loads. however, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum. data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 11/15 rev 2b recommended usage analog input the analog inputs to the cdk2308 is a switched capacitor track-and-hold amplifer optimized for differential opera - tion. operation at common mode voltages at mid sup - ply is recommended even if performance will be good for the ranges specifed. the cm_ext pin provides a voltage suitable as common mode voltage reference. the internal buffer for the cm_ext voltage can be switched off, and driving capabilities can be changed by using the cm_ext - bc control input. figure 2 shows a simplifed drawing of the input network. the signal source must have suffciently low output imped - ance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may im - prove performance. the resistors form a low pass flter with the capacitor, and values must therefore be deter - mined by requirements for the application. figure 2. input confguration dc-coupling figure 3 shows a recommended confguration for dc- coupling. note that the common mode input voltage must be controlled according to specifed values. preferably, the cm_ext output should be used as a reference to set the common mode voltage. the input amplifer could be inside a companion chip or it could be a dedicated amplifer. several suitable single ended to differential driver amplifers exist in the market. the system designer should make sure the specifcations of the selected amplifer is adequate for the total system, and that driving capabilities comply with the cdk2308 input specifcations. figure 3. dc-coupled input detailed confguration and usage instructions must be found in the documentation of the selected driver. ac-coupling a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 4 shows a recommended confguration using a transformer. make sure that a transformer with suffcient linearity is selected, clk_ext n-13 +f0 +f2 +f1 +f4 +f + figure 1. timing diagram pf n-13 n-12 n-11 n-10 n-9 n-8 data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 12/15 rev 2b and that the bandwidth of the transformer is appropriate. the bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to keep phase mismatch between the differential adc inputs small for good hd2 performance. this type of transformer coupled input is the preferred confguration for high fre - quency signals as most differential amplifers do not have adequate performance at high frequencies. magnetic coupling between the transformers and pcb traces may impact channel crosstalk, and must hence be taken into account during pcb layout. if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated prop - erly at the source side, they are refected and will add to the input signal at the adc input. this could reduce the adc performance. to avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. if this problem could not be avoided, the circuit in figure 6 can be used. figure 4. transformer-coupled input figure 5 shows ac-coupling using capacitors. resistors from the cm_ext output, rcm, should be used to bias the differential input signals to the correct voltage. the series capacitor, ci, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. figure 5. ac-coupled input note that startup time from sleep mode and power down mode will be affected by this flter as the time required to charge the series capacitors is dependent on the flter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc not are effectively terminated at the signal source, the input network of fgure 8 can be used. the confguration in fgure 8 is designed to at - tenuate the kickback from the adc and to provide an in - put impedance that looks as resistive as possible for fre - quencies below nyquist. values of the series inductor will however depend on board design and conversion rate. in some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pf) may improve adc per - formance further. this capacitor attenuate the adc kick- back even more, and minimize the kicks traveling towards the source. however, the impedance match seen into the transformer becomes worse. figure 6. alternative input network clock input and jitter considerations typically high-speed adcs use both clock edges to generate internal timing signals. in the cdk2308 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% is acceptable. the input clock can be supplied in a variety of formats. the clock pins are ac-coupled internally, and hence a wide common mode voltage range is accepted. differential clock sources as lvds, lvpecl or differential sine wave can be connected directly to the input pins. for cmos inputs, the clkn pin should be connected to ground, and the cmos clock signal should be connected to clkp. for differential sine wave clock input the amplitude must be at least 800mv pp . 33 33 r t 47 pf pf 120nh 120nh 33 33 r t 68 220 optional 1:1 data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 13/15 rev 2b the quality of the input clock is extremely important for high-speed, high-resolution adcs. the contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1. snr jitter = 20 ? log (2 ? ? f in ? t ) where f in is the signal frequency, and t is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable per - formance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock refer - ences (e.g. crystal oscillators with good jitter specifcations) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter per - formance is obtained with lvds or lvpecl clock with fast edges. cmos and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be retimed with a low jitter master clock as the last operation before it is applied to the adc clock input. digital outputs digital output data are presented on parallel cmos form. the voltage on the ov dd pin set the levels of the cmos outputs. the output drivers are dimensioned to drive a wide range of loads for ov dd above 2.25v, but it is rec - ommended to minimize the load to ensure as low tran - sient switching currents and resulting noise as possible. in applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the adc chip. the timing is described in the timing diagram section. note that the load or equivalent delay on clk_ext always should be lower than the load on data outputs to ensure suffcient timing margins. the digital outputs can be set in tristate mode by setting the oe_n signal high. the cdk2308 employs digital offset correction. this means that the output code will be 4096 with the positive and negative inputs shorted together(zero differential). how - ever, small mismatches in parasitics at the input can cause this to alter slightly. the offset correction also results in possible loss of codes at the edges of the full scale range. with no offset correction, the adc would clip in one end before the other, in practice resulting in code loss at the opposite end. with the output being centered digitally, the output will clip, and the out of range fags will be set, before max code is reached. when out of range fags are set, the code is forced to all ones for over-range and all zeros for under-range. data format selection the output data are presented on offset binary form when dfrmt is low (connect to ov ss ). setting dfrmt high (connect to ov dd ) results in 2s complement output format. details are shown in table 1 on page 14. reference voltages the reference voltages are internally generated and buff - ered based on a bandgap voltage reference. no external decoupling is necessary, and the reference voltages are not available externally. this simplifes usage of the adc since two extremely sensitive pins, otherwise needed, are removed from the interface. operational modes the operational modes are controlled with the pd_n and slp_n pins. if pd_n is set low, all other control pins are overridden and the chip is set in power down mode. in this mode all circuitry is completely turned off and the internal clock is disabled. hence, only leakage current contributes to the power down dissipation. the startup time from this mode is longer than for other idle modes as all references need to settle to their fnal values before normal operation can resume. the slp_n bus can be used to power down each channel independently, or to set the full chip in sleep mode. in this mode internal clocking is disabled, but some low band - width circuitry is kept on to allow for a short startup time. however, sleep mode represents a signifcant reduction in supply current, and it can be used to save power even for short idle periods. the input clock should be kept running in all idle modes. however, even lower power dissipation is possible in power down mode if the input clock is stopped. in this case it is important to start the input clock prior to enabling active mode. data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 14/15 rev 2b table 1: data format description for 2v pp full scale range differential input voltage (ipx - inx) output data: dx_9 : dx_0 (dfrmt = 0, offset binary) output data: dx_9 : dx_0 (dfrmt = 1, 2s complement) 1.0 v 11 1111 1111 01 1111 1111 +0.24mv 10 0000 0000 00 0000 0000 -0.24mv 01 1111 1111 11 1111 1111 -1.0v 00 0000 0000 10 0000 0000 mechanical dimensions qfn-64 package a a2 a3 a1 1 1.14 d d1 e e1 1.14 pin 1 id dia. 0.20 pin 1 id 0.05 dia. seating plane 0.45 g l l b e d2 e2 a c b aaa c a ccc c bbb c a aaa c b bbb c b f 0.10 m c b a notes: 1 . all dimensions are in millimeters. 2. die thickness allowable is 0.305mm maximum (.012 inches maximum) 3. dimensioning & tolerances conform to asme y14.5m. -1994. 4. dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip. 5. the pin #1 identifier must be placed on the top surface of the package by using indentation mark or other feature of package body. 6. exact shape and size of this feature is optional. 7. package warpage max 0.08mm. 8. applied for exposed pad and terminals. exclude embedding part of exposed pad from measuring. 9. applied only to terminals. 10. package corners unless otherwise specipied are r0.1750.025mm. top view bottom view side view inches millimeters symbol min typ max min typ max a ? ? 0.035 ? ? 0.9 a 1 0.00 0.0004 0.002 0.00 0.01 0.05 a 2 ? 0.026 0.028 ? 0.65 0.7 a 3 0.008 ref 0.2 ref b 0.008 0.010 0.012 0.2 0.25 0.30 d 0.354 bsc 9.00 bsc d 1 0.354 bsc 8.75 bsc d 2 0.197 0.205 0.213 5.0 5.2 5.4 e 0.354 bsc 9.00 bsc e 1 0.344 bsc 8.75 bsc e 2 0.197 0.205 0.213 5.0 5.2 5.4 f 0.05 ? ? 1.3 ? ? g 0.0096 0.0168 0.024 0.24 0.42 0.6 l 0.012 0.016 0.020 0.3 0.4 0.5 e 0.020 bsc 0.50 bsc 1 0 ? 12 0 ? 12 tolerance of form and position aaa 0.10 0.004 bbb 0.10 0.004 ccc 0.05 0.002 data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b
?2009-2013 exar corporation 15/15 rev 2b data sheet cdk2308 dual, 20/40/65/80msps, 10-bit analog-to-digital converters rev 2b for further assistance: exar corporation headquarters and sales offces 48720 kato road tel.: +1 (510) 668-7000 fremont, ca 94538 - usa fax: +1 (510) 668-7001 www.exar.com notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specifc application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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